Placement and Routing for N Embedded Programmable Logic

As SoC design enters into mainstream usage, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. These cores are like any other IP in the SoC design methodology, except that their function can be changed after fabrication. In many cases, non-rectangular programmable logic cores are required, either to better mesh with the other IP cores, or because of I/O constraints. In order to use programmable logic cores, placement and routing algorithms are required to implement user circuits on the core. Existing placement and routing algorithms that target programmable logic were optimized for stand-alone FPGA’s which are invariably square or rectangular. In this paper we show that these algorithms do not work well when targetting non-rectangular programmable logic cores, and we present enhancements to existing placement and routing algorithms that allow the algorithms to better target these cores. It is shown that the new algorithms lead to a 12% critical path improvement for “U”-shaped cores, and a 4% improvement for “O”-shaped cores. The density and speed penalty for using these non-rectangular cores is significant, compared to square cores, however, we show that the penalty would be significantly larger if the original algorithms were used. 1. In Re achi main tech these One (SoC desig intel sour Thes bloc func know com N and alwa then not d requ desig meth one ASIC Logic CPU Core MixedSignal Core